1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and the manufacture thereof and, more particularly, to a nonvolatile semiconductor memory device having a memory transistor constituted by a floating gate electrode and a control gate electrode and a method of manufacturing the same.
2. Description of the Related Art
EPROMs and E.sup.2 PROMs are well known as nonvolatile semiconductor memory devices capable of rewriting storage data.
EPROMs and E.sup.2 PROMs have memory transistors, each constituted by a floating gate electrode in an electrically floating state and a floating gate electrode functioning as a word line, in their memory cell portions. Storage data is determined by the charge state of each floating gate electrode and is replaced with storage data of "1" or "0" in accordance with the ON/OFF state of the corresponding memory transistor.
Floating gate electrodes and control gate electrodes are formed by the following method. A first polysilicon layer is deposited on a first gate insulating film. Cell slits are formed in the first polysilicon layer to isolate floating gate electrodes in units of memory cells. A second gate insulating film is formed on the resultant structure, and a second polysilicon layer subsequently is deposited. The second polysilicon layer is then patterned in the form of a word line by using a photoresist. At the same time, the first polysilicon layer is etched in a self-aligned manner by using this photoresist with the form of a word line, thus forming floating gate electrodes isolated in units of memory cells (a conventional EPROM).
A method of forming floating electrodes to be self-aligned with a word line in the above-described manner has generally been employed.
In addition, a word line also serves as a control gate electrode in each memory cell.
FIGS. 1 and 2 are plan and sectional views in a process in which floating gates are formed in a self-aligned manner with respect to a word line. FIG. 2 is a sectional view taken along a line M--Ma in FIG. 1.
As shown in FIGS. 1 and 2, field oxidation films 2 are formed on the upper surface of a substrate 1. Referring to FIGS. 1 and 2, reference numeral 3 denotes source regions; and 4, drain regions. Floating gate electrodes 6 are formed between these regions through first gate insulating films 5. The floating gate electrodes 6 are formed to be isolated from each other in units of memory cells. A word line 8 is formed on the floating gate electrodes 6 through second gate insulating films 7. This word line 8 extends over the respective memory cells adjacent to each other in the channel width direction and serves as a control gate electrode in each memory cell. Reference numeral 9 denotes contact hole regions with respect to the drain regions.
Drawbacks of this conventional structure will be described below.
The first drawback of the conventional structure is that the breakdown voltage of the second gate insulating film 7 between the control gate electrode (word line) 8 and the floating gate electrode 6 is decreased.
This problem is posed because the second gate insulating films 7 are formed in a state wherein cell slits 10 are formed to isolate the floating gate electrodes 6 from each other, which are formed by the first polysilicon layer on the memory cells adjacent to each other in the column direction.
More specifically, if oxidation is performed while the cell slits 10 are formed, since the oxidation rate of a corner portion, of the first polysilicon layer, indicated by a circle 11 in FIG. 2 is lower than that of a flat portion, the second gate insulating film 7 formed in the corner portion is thinner than that formed on the flat portion.
In addition, with this decrease in film thickness, an electric field tends to concentrate on the corner portion of the floating gate electrode 6 since the corner portion is a projection.
The above-described two points synergistically act to decrease the breakdown voltage of the second gate insulating film 7. Especially, the electric field concentration at the corner portion of the floating gate electrode 6 causes a considerable decrease in breakdown voltage because the control gate electrode 8 is arranged to oppose the floating gate electrode 6.
Once a breakdown of the second insulating film 7 occurs, the control gate electrode 8 and the floating gate electrode 6 are electrically connected to each other. As a result, the potential of the control gate electrode 6 is directly applied to the first gate insulating film 5.
The degree of damage to the first gate insulating film 5 varies depending on its thickness. In an E.sup.2 PROM including a tunnel insulating film having a thickness of, e.g., 100 .ANG. or less, the damage to this tunnel insulating film is great.
In an E.sup.2 PROM, if a breakdown of a second gate insulating film occurs, a voltage (e.g., about 20 V) applied to a control gate electrode is directly applied to a tunnel insulating film. The tunnel insulating film is then broken down. As a result, the control gate (word line) and a substrate are short-circuited. If a short circuit of the control gate electrode (word line) and the substrate occurs, the damage caused by the breakdown of the second gate insulating film is not limited to only one bit and memory cells corresponding to one word line, e.g., eight bits, i.e., one byte, cannot perform write and erase operations any longer.
As described above, in a nonvolatile semiconductor memory device incorporating memory cells each consisting of a floating gate and a control gate, one defect may cause a large number of defects. Therefore, each element must be produced in strict conditions.
The second drawback of the conventional structure is associated with the process of forming the cell slits 10 in the first polysilicon layer so as to isolate the floating gate electrodes 6, of the memory cells adjacent to each other in the column direction, from each other.
In the process in question, the first polysilicon layer is partially etched to form the cell slits 10. The problem is that after the second gate insulating film 7 is formed by thermal oxidation of the first polysilicon layer, the second polysilicon layer, the second gate insulating film 7, and the first polysilicon layer are simultaneously etched to pattern a word line and floating gates.
In such a process, no first polysilicon layer is left in the regions where the cell slits 10 are formed. In a region where the cell slit 10 is formed and no word line 8 is present, the field oxidation film 2 is locally reduced in thickness. This region where the decrease in film thickness occurs is denoted by reference numeral 12 in FIG. 1.
More specifically, in this thickness-reduced region 12, when the second gate insulating film 7 and the floating gate electrode 6 (first polysilicon layer) are partially etched, the upper surface of the field oxidation film 2 is also etched to cause a great reduction in film thickness of the film 2.
In the worst case, the thickness of the field oxidation film 2 in the thickness-reduced region 12 is reduced to about 1/3 the initial film thickness.
This reduction of thickness, if occurs, the elements cannot be electrically isolated completely.
The above-described two drawbacks may be temporarily eliminated by stricter manufacturing process management. However, fundamental measures are required, for the future, in terms of a nonvolatile semiconductor memory device and a method of manufacturing the same.